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Sheet目录3882

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PIC18FXX39

DS30485A-page 178

Preliminary

2002 Microchip Technology Inc.

17.3.2

USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled

setting

either

enable

bit

SREN

(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, only a single word

is received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

To set up a Synchronous Master Reception:

Initialize the SPBRG register for the appropriate

baud rate (Section 17.1).

Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

Ensure bits CREN and SREN are clear.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

the enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 17-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

FIGURE 17-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x

0000 000u

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

—

TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

—

TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

—

TMR2IP TMR1IP 0000 0000 0000 0000

RCSTA

SPEN

RX9

SREN

CREN ADDEN

FERR

OERR

RX9D

0000 -00x

RCREG

USART Receive Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

SPBRG

Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

CREN bit

RC7/RX/DT pin

RC6/TX/CK pin

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

'0'

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

'0'

Q1 Q2 Q3 Q4

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.

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